Efinix, Inc.

Manufacturer Overview

Efinix, Inc.
(Efinix)

At the core of EFINIX FPGAs is the disruptive Quantum® fabric, which delivers advantages in power, performance, and area over conventional FPGA technologies.
EFINIX Titanium FPGAs are designed to enable new applications and accelerate innovation in mainstream markets. With densities ranging from 4K to 2 million logic elements (LEs), EFINIX FPGAs are ready to address a wide variety of design challenges, including custom logic, compute acceleration, machine learning, and deep learning.

Product Information

FPGA

Titanium FPGAs

Product Logo

・A broad and highly scalable FPGA platform for high-performance general-purpose applications
・Provides an optimal balance of performance, power efficiency, and compact design
・Flexible XLR architecture supporting a wide range of markets and applications

Feature	Ti35	Ti60	Ti90	Ti120	Ti165	Ti180	Ti240	Ti375
Logic Elements(LEs)	36,176	62,016	92,534	123,379	162,800	176,256	236,888	370,137
10K RAM blocks(Mb)	1.53	2.62	6.88	9.18	12.1	13.11	17.62	27.53
DSP blocks	93	160	336	448	590	640	860	1,344
PLLs	4	4	8	8	12	8	12	12
High-voltage I/O	27	27	74	74	51	74	51	51
High-speed I/O	142	142	210	210	176	210	176	176
MIPI D-PHY,support CSI-2/DSI(Gbps)	1.5	1.5	1.5	1.5	1.5	1.5	1.5	1.5
LPDDR4/4x	ー	ー	1 x32	1 x32	1 x32	1 x32	1 x32	1 x32
MIPI D-PHY 2.5Gbps(Hard IP)	ー	ー	4 TX 4 RX	4 TX 4 RX	ー	4 TX 4 RX	ー	ー

Package	Pitch(mm)	Size(mm)
64-ball WLCSP	0.4	3.5×3.4
100-ball FBGA(1)	0.5	5.5×5.5
225-ball FBGA	0.65	10×10
256-ball FBGA	0.8	13×13
361-ball FBGA	0.65	13×13
400-ball FBGA	0.8	16×16
484-ball FBGA(2)	0.65	15×15
484-ball FBGA	0.8	18×18
529-ball FBGA	0.8	19×19

(1) The 100-pin package for Ti35 and Ti60 FPGAs is available as either a standard package containing only the FPGA or as a SiP containing the FPGA together with one SPI flash device and one HyperRAM device.
(2) The 484-pin package for Ti180 is a SiP containing the FPGA together with one LPDDR DRAM device.

Titanium Edge FPGAs

Product Logo

・A compact, low-power platform designed for intelligent edge systems
・Robust operation enabled by enhanced HSIO with SEU detection and correction and ultra-low static power consumption
・Optimized for real-time edge applications where size, thermal efficiency, and power consumption are critical

Feature	Ti40	Ti70	Ti95	Ti125
Logic Elements(LEs)	38,925	68,218	93,200	122,792
10K RAM blocks(Mb)	1.53	2.62	4.5	5.9
DSP blocks	100	160	210	288
PLLs	4	4	7	7
High-voltage I/O	36	36	36	36
High-speed I/O(MIPI 1.5Gbps)	–	–	95	95
High-speed I/O(MIPI 2.5Gbps)	147	147	110	110

Package	Pitch(mm)	Size(mm)
64-ball WLCSP	0.4	3.5×3.4
100-ball FBGA(3)	0.5	5.5×5.5
225-ball FBGA(4)	0.5	8×8
225-ball FBGA	0.65	10×10
324-ball FBGA	0.8	15×15

(3) The 100-pin package for the Ti70 FPGA is available as either a standard package containing only the FPGA or as a SiP containing the FPGA together with one SPI flash device and one HyperRAM device.
(4) The 225-pin package for the Ti125 FPGA is available as either a standard package containing only the FPGA or as a SiP containing the FPGA together with one SPI flash device and two HyperRAM devices.

Titanium Transceiver FPGAs

Product Logo

・Optimized for high-throughput and data-intensive workloads
・Advanced serial interfaces enabling high-speed data transfer
・Designed for communications, networking, video, and high-performance embedded systems

Feature	Ti85	Ti135	Ti140	Ti165	Ti240	Ti260	Ti375	Ti450	Ti660	Ti800	Ti1250	Ti1600	Ti2000
Logic Elements(LEs)	83,232	132,192	142,300	162,800	236,888	264,384	370,137	447,890	656,916	796,262	1,233,020	1,578,000	1,974,067
10K RAM blocks(Mb)	6.18	9.83	10.6	12.1	17.62	19.7	27.53	26.6	38.9	47.2	73.1	93.6	117
DSP blocks	300	480	510	590	860	960	1,344	862	1,260	1,536	2,380	3,050	3,808
PLLs	9	9	12	12	12	12	12	12	12	12	12	12	12
High-voltage I/O	84	84	150	103	103	150	103	180	180	180	180	180	180
High-speed I/O	139	139	160	234	234	160	234	300	300	300	300	300	300
MIPI D-PHY, support CSI-2/DSI (Gbps)	1.5	1.5	2.5	1.5	1.5	2.5	1.5	2.5	2.5	2.5	2.5	2.5	2.5
LPDDR4/4x	x32	x32	2×32	2 x32	2 x32	2 x32	2 x32	3 x32	3 x32	3 x32	4 x32	4 x32	4 x32
MIPI D-PHY 2.5 Gbps (Hard IP)	2TX 2RX	2TX 2RX	–	3TX 3RX	3TX 3RX	–	3TX 3RX	–	–	–	–	–	–
16 Gbps Transceivers	x8	x8	x16	x16	x16	x16	x16	–	–	–	–	–	–
25.8 Gbps Transceivers	–	–	–	–	–	–	–	x24	x24	x24	x40	x40	x40
PCle® Gen4 (16G)	1 x4	1 x4	2 x4	2 x4	2 x4	2 x4	2 x4	2 x8	2 x8	2 x8	3 x8	3 x8	3 x8
Hardened Ouad-Core RISC-V Processor	RV32	RV32	RV64	RV32	RV32	RV64	RV32	RV64	RV64	RV64	RV64	RV64	RV64

Package	Pitch(mm)	Size(mm)
441-ball FBGA	0.5	11×11
484-ball FBGA	0.8	18×18
576-ball FBGA(5)	0.65	16×16
676-ball FBGA	0.65	18×18
676-ball FBGA	0.8	22×22
900-ball FBGA	0.8	25×25
1156-ball FBGA	1.0	35×35
1521-ball FBGA	1.0	40×40

(5) The Ti135 576-ball FBGA is available either as a standard FPGA package or as a SiP integrating SPI flash and LPDDR4/4X DRAM.

Small Packages

Titanium™ FPGAs are available in ultra-small packages as small as 3.5mm x 3.4mm WLCSP, making them ideal for highly integrated applications.

Hard Controllers

Hardened MIPI D-PHY and DDR DRAM controllers support IoT devices, thermal cameras, industrial cameras, robotics, and smart devices.

SEU Detection

Titanium™ devices monitor device integrity, enabling applications to recover from random SEU events and maximize system uptime.

Bitstream Security

Bitstream authentication prevents unauthorized tampering, while bitstream encryption protects the security of your design.

Topaz FPGA

A new device family optimized for mass production is now available.
Topaz™ FPGAs combine a highly efficient architecture with commonly used features and protocols such as PCIe Gen3, MIPI, LPDDR4, and LVDS, enabling deployment at scale.

Feature	Tz50	Tz75	Tz100	Tz110	Tz170	Tz200	Tz325
Logic Elements (LEs) (LE)	52,160	75,520	101,440	120,584	161,008	215,360	326,080
10K RAM blocks (Mb) (Mb)	2.4	5.34	6.32	6.41	11.14	15.77	19.22
DSP blocks	140	264	312	320	544	840	1,008
PLLs	4	9	9	8	8	12	12
High-voltage I/0	27	84	84	74	74	51	51
High-speed I/0	142	139	139	200	200	176	176
LPDDR4	ー	1 x32	1 x32	1 x32	1 x32	2 x32	2 x32
MIPI D-PHY 2 Gbps	ー	2 RX 2 TX	2 RX 2 TX	4 RX 4 TX	4 RX 4 TX	1 RX 1 TX	1 RX 1 TX
12.5 Gbps transceivers	ー	2 x4	2 x4	ー	ー	4 x4	4 x4
Hardened RISC-V block	ー	Quad Core	Quad Core	ー	ー	Quad Core	Quad Core
PCle® Gen3 (8G)	ー	1 x4	1 x4	ー	ー	2 x4	2 x4

Package	Pitch(mm)	Size(mm)
100-ball FBGA	0.5	5.5×5.5
225-ball FBGA	0.65	10×10
256-ball FBGA	0.8	13×13
361-ball FBGA	0.65	13×13
400-ball FBGA	0.8	16×16
441-ball FBGA	0.5	11×11
484-ball FBGA	0.8	18×18
529-ball FBGA	0.8	19×19
576-ball FBGA	0.65	16×16
676-ball FBGA	0.8	22×22
676-ball FBGA	0.65	18×18
900-ball FBGA	0.8	25×25

Excellent Utilization

The Topaz™ architecture is designed to pack more logic into XLR cells, enabling more functionality to be implemented.

Protocol Support

Topaz™ FPGAs support commonly used protocols such as LVDS, MIPI, Ethernet, and PCIe Gen3, making them suitable for applications including machine vision, robotics, and printers.

Easy-to-Use Packages

Topaz™ FPGAs are available in a wide range of BGA packages that can be easily integrated into systems.

Seamless Migration

If you need to improve design performance or add more logic, you can easily migrate from Topaz™ to Titanium™ FPGAs.

Trion FPGA

Product Logo

The Trion® platform is manufactured using the SMIC 40nm LL process and offers logic densities ranging from 4,000 to 200,000 logic elements (LEs), with integrated standard interfaces such as GPIO, PLL, oscillators, MIPI, DDR, and LVDS. Trion FPGAs target the general-purpose custom logic market, including mobile devices, IoT, general consumer products, industrial equipment, and medical devices. They also support rapidly growing markets such as deep learning and compute accelerators at the edge.

Feature	T4	T8	T13	T20	T35	T55	T85	T120
Logic Elements (LEs)	3,888	7,384	12,828	19,728	31,680	54,195	84,096	112,128
Mask Programmable Memory (MPM)					ー	ー	ー	ー
Embedded RAM Bits (kb)	77	123	727	1,044	1,475	2,765	4,055	5,407
Embedded 5K RAM blocks	15	24	142	204	288	540	792	1,056
18×18 Multipliers	4	8	24	36	120	150	240	320
PLLs	1	5	5	7	7	8	8	8
LVDS (TX, RX)	ー	6, 6	13, 13	20, 26	20, 26	52, 52	52, 52	52, 52
DDR3, LPDDR3, LPDDR2 (up to 1066 Mbps)	ー	ー	ー	x16	x16	x32	x32	x32
MIPI 4-lane DPHY with built-in CSI-2 controller	ー	ー	2 RX 2 TX	2 RX 2 TX	2 RX 2 TX	3 RX 3 TX	3 RX 3 TX	3 RX 3 TX

Package	Pitch(mm)	Size(mm)	GPIO (1)	PLLS	SPI Flash (Mbit)	LVDS Pairs TX, RX	MIPI CSI-2 TX, RX(1)	DDR DRAM(1)
49-ball FBGA	0.4	3×3	33	1
80-ball WLCSP	0.4	4.5×3.6	33	3			1,1
81-ball FBGA	0.5	5×5	55	1
100-pin LQFP	0.5	14×14	65	5	16	4,4
144-pin LQFP	0.5	20×20	97	5		6,6
169-ball FBGA	0.65	9×9	73	5		8,12	2,2
256-ball FBGA	0.8	13×13	195	5		13,13
256-ball FBGA	0.8	13×13	191	7		10,18
324-ball FBGA	0.65	12×12	130	7		20,26	2,2	x8, x16
400-ball FBGA	0.8	16×16	230	7		20,26		x8, x16
484-ball FBGA	0.8	18×18	256	8		40,40		x16, x32
576-ball FBGA	0.65	16×16	278	8		52,52	3,3	x16, x32

(1) The MIPI and DDR interface have dedicated I/O; therefore; the GPIO number does not include the I/0 count for those interfaces.

Small Packages

Trion FPGAs are available in packages as small as 4.5mm x 3.6mm WLCSP, making them ideal for highly integrated applications.

MIPI CSI-2 Controller

The hardened controller for the widely used MIPI CSI-2 interface supports IoT devices, thermal cameras, industrial cameras, robotics, and smart devices.